1. Field of the Invention
Generally, the present disclosure relates to the fabrication of highly sophisticated integrated circuits including advanced transistor elements that comprise strain-inducing semiconductor alloys and gate structures of increased capacitance including a high-k gate dielectric and a metal-containing cap layer.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. In a wide variety of integrated circuits, field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced for forming field effect transistors, wherein, for many types of complex circuitry, MOS technology is one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length, and associated therewith the reduction of channel resistivity, which in turn causes an increase of gate resistivity due to the reduced dimensions, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Presently, the vast majority of integrated circuits are based on silicon due to its substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the last 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations designed for mass products. One reason for the dominant role of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes, as are required, for example, during anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a base material of a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon or other materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has been continuously decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current while also requiring enhanced capacitive coupling of the gate electrode to the channel region. Thus, the thickness of the silicon dioxide layer has to be correspondingly decreased to provide the required capacitance between the gate and the channel region. For example, a channel length of approximately 80 nm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although usage of high speed transistor elements having an extremely short channel may be restricted to high speed signal paths, whereas transistor elements with a longer channel may be used for less critical circuit portions, such as storage transistor elements, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range of 1-2 nm that may not be compatible with requirements for many types of circuits, even if only transistors in speed critical paths are formed on the basis of an extremely thin gate oxide.
Therefore, replacing silicon dioxide as the material for gate insulation layers has been considered, particularly for extremely thin silicon dioxide gate layers. Possible alternative materials include materials that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide layer. It has thus been suggested to replace silicon dioxide with high permittivity materials such as tantalum oxide (Ta2O5), with a k of approximately 25, strontium titanium oxide (SrTiO3), having a k of approximately 150, hafnium oxide (HfO2), HfSiO, zirconium oxide (ZrO2) and the like.
Additionally, transistor performance may be increased by providing an appropriate conductive material for the gate electrode so as to replace the usually used polysilicon material, since polysilicon may suffer from charge carrier depletion at the vicinity of the interface to the gate dielectric, thereby reducing the effective capacitance between the channel region and the gate electrode. Thus, a gate stack has been suggested in which a high-k dielectric material provides an increased capacitance based on the same thickness as a silicon dioxide layer, while, additionally, leakage currents are kept at an acceptable level. On the other hand, the non-polysilicon material, such as titanium nitride and the like, may be formed so as to connect to the high-k dielectric material, thereby substantially avoiding the presence of a depletion zone.
After forming sophisticated gate structures including a high-k dielectric and a metal-based gate material, however, high temperature treatments may be required, which may result in a shift of the work function and a reduction of the permittivity of the gate dielectric, which may also be associated with an increase of layer thickness, thereby offsetting many of the advantages of the high-k dielectric in combination and the metal material. It is believed that the deterioration of the high-k metal gate is substantially caused by the incorporation of oxygen and a respective oxygen diffusion within the high-k dielectric material, wherein the oxygen diffusion may be fed by oxygen contained in the ambient that may come into contact with the high-k dielectric during the processing of the devices. Since, for instance, hafnium- and zirconium-based oxides grow very fast due to the high affinity to oxygen diffusion even at moderate temperatures, a significant modification of the characteristics of the high-k dielectric material may be observed, for instance, an increased layer thickness and thus a reduced dielectric constant, which may be even further pronounced at moderately high temperatures of approximately 950-300°, as may typically be used during activation treatments and the like.
In addition to a significant modification of the high-k dielectric material, the work function of the metal in the gate stack may also be shifted towards the center of the band gap, thereby modifying the threshold voltage of respective transistors. Due to the high oxygen affinity of the high-k dielectric material and due to the exposure to wet chemical etch procedures and cleaning processes, the gate stack is usually encapsulated after the patterning process in order to enhance stability of the high-k dielectric material and the respective metals in the gate stack. For this purpose, silicon nitride has proven to be a promising material due to its oxygen blocking characteristics. Hence, in typical conventional process flows, a silicon nitride liner with a thickness in the range of approximately 1-5 nm may be formed on exposed surface areas of the patterned high-k gate stack, wherein appropriate deposition techniques are used so as to not unduly affect device characteristics and/or the subsequent manufacturing steps. For example, well-established low pressure chemical vapor deposition (LPCVD) techniques may be applied for forming the silicon nitride liner.
In addition to providing sophisticated gate electrode structures by using high-k dielectric materials and metal-containing gate electrode materials, other approaches have been developed in order to enhance transistor performance for a given gate length and a thickness of a gate dielectric material. For example, by creating a certain strain component in the channel region of the transistor elements, the charge carrier mobility and thus the overall conductivity of the channel may be enhanced. For a silicon material having a standard crystallographic configuration, i.e., a (100) surface orientation with the channel length direction oriented along a <110> equivalent direction, the creation of a tensile strain component in the current flow direction may enhance conductivity of electrons, thereby improving transistor performance of N-channel transistors. On the other hand, generating a compressive strain component in the current flow direction may increase hole mobility and thus provide superior conductivity in P-channel transistors. Consequently, a plurality of strain-inducing mechanisms have been developed in the past which may per se require a complex manufacturing sequence for implementing the various strain-inducing techniques. For example, one promising approach that is frequently applied is the incorporation of a compressive strain-inducing silicon/germanium alloy in the drain and source areas of P-channel transistors. For this purpose, in an early manufacturing stage, cavities are formed selectively adjacent to the gate electrode structure of the P-channel transistor, while the N-channel transistors are covered by a spacer layer. Additionally, the gate electrode of the P-channel transistor has to be encapsulated in order to not unduly expose the gate electrode material to the etch ambient for forming the cavities and also for providing an efficient growth mask during the selective epitaxial growth process, in which the silicon/germanium alloy may be grown on a crystalline substrate material, while a significant deposition of the alloy on dielectric surface areas may be suppressed by appropriately selecting the corresponding process parameters. After forming the strain-inducing silicon/germanium alloy, the corresponding spacer structure and a cap layer encapsulating the gate electrode of the P-channel transistor may be removed along with the spacer layer that covers the N-channel transistors. Thereafter, the further processing may be continued by forming drain and source regions so as to complete the basic transistor configuration.
The above-described strain-inducing mechanism is a very efficient concept for improving transistor performance of P-channel transistors and thus a combination with sophisticated gate electrode structures on the basis of a high-k dielectric material is highly desirable. The efficiency of the finally obtained strain component in the channel region of the transistor, however, strongly depends on the internal strain level of the semiconductor alloy and from the lateral offset from the channel region. Since the material composition may be restricted to a concentration of approximately 30 atomic percent germanium in a silicon/germanium alloy based on currently available sophisticated selective epitaxial deposition recipes, further improvement of the strain may require a reduction of the lateral offset, which in turn, however, is correlated with the thickness of any protective dielectric materials on sidewalls of the gate electrode structure. Consequently, the protective silicon nitride liner, which may be provided to enhance integrity of the sensitive gate electrode structure during the further processing for completing the transistor configuration, may be reduced in thickness, for instance in combination with any additional offset spacer elements that may be required, which may, however, result in severe yield losses due to material loss in the gate electrode structure. Without intending to restrict the present application to the following explanation, it is believed that any patterning irregularities, in particular at the foot of complex gate electrode structures, may result in inferior coverage of this area when further reducing the thickness of the silicon nitride liner material. That is, upon patterning the complex gate layer stack, a lateral increase of gate length may frequently occur at the foot of the gate electrode structures, at least for one type of transistor element, which may thus result in a reduced degree of coverage by the silicon nitride material, thereby increasing the probability of an interaction with aggressive chemical agents during the further processing of the semiconductor device. For instance, an SPM solution (a mixture of sulfuric acid and hydrogen peroxide) has been proven to be a very efficient cleaning agent after encapsulating the gate electrode structure and prior to the further processing in order to remove contaminants, metal residues and the like. Omitting the cleaning step in this manufacturing stage or providing a less efficient cleaning recipe may significantly increase overall defectivity, which may thus result in a significant yield loss. On the other hand, the inferior degree of coverage at the foot of the gate electrode structures of at least some transistors may result in an interaction with the sulfuric acid, which has the tendency of removing significant amounts of the titanium nitride material, even if only very minute non-covered surface portions thereof are available for an interaction with the sulfuric acid. While an increase of protective silicon nitride material on sidewalls of the gate electrode structures may significantly reduce the probability of a titanium nitride loss during a cleaning process performed on the basis of SPM, the resulting loss in performance of transistors, such as P-channel transistors, due to a less efficient strain-inducing mechanism, may make this solution less than desirable. On the other hand, omitting the SPM-based cleaning process may not represent a viable option due to the drastically increased defect rate during the further processing of the semiconductor devices.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.